Silicon-Proven
Arteris? FlexLLI digital controller IP is the industry’s first and?only silicon-proven implementation?of the MIPI Low Level Interface (LLI) specification.
LLI Use Models
Arteris FlexLLI digital controller IP can connect two chips together to create a single “virtual chip”, with both chips sharing a single DRAM. LLI’s initial expected purpose is to connect a mobile phone applications processor to a mobile phone modem.
The ~80ns round-trip latency of an LLI connection is fast enough for the modem to share the application processor’s RAM. This enables the phone manufacturer to remove the modem’s dedicated RAM chip from the phone’s bill of materials (BOM).
FlexLLI can also be used in non-mobile applications where low latency and high bandwidth between chips is required, such as co-processing and companion chip applications.
FlexLLI does not require a runtime software stack, unlike other standards like USB and PCIe.
BoM Cost and PCB Area Benefits
FlexLLI Advantages |
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|---|---|
| BoM Cost Savings | ~$1.25 256Mb LPDDR1 ~$2.00 512Mb LPDDR2 (cost estimates for 2012) |
| PCB Area Savings | 72 mm2 (8x9mm) for LPDDR1 115 mm2 (10×11.5mm) for LPDDR2 |
Using Arteris FlexLLI saves a mobile phone vendor $1 to 2 from RAM cost savings alone. This savings is even larger when one includes the benefits of reduced board area.
FlexLLI Benefits to SoC Developers
FlexLLI Advantages |
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|---|---|
| Lowest Risk | ? FlexLLI is the ONLY silicon-proven LLI digital IP. ? Arteris was a major contributor to the MIPI LLI specification. |
| Easiest | Shares FlexNoC’s automated environment for fast LLI configuration and verification setup |
| Most Flexible | Extensive configuration options for easier integration and fastest time to market |
In addition to being the lowest risk option for implementing MIPI LLI, Arteris FlexLLI is also the easiest and fastest to implement because it shares Arteris FlexNoC’s automated design environment for fast configuration and verification setup. FlexLLI also offers extensive configuration options for quicker SoC integration and fastest time to market.
Arteris Experience and Innovation
Arteris is a major contributor to the MIPI Low Latency Interface specification and has extensive experience in network on chip technology and SoC interconnect IP with its FlexNoC product line. Arteris helped pioneer low latency interconnect IP, working with Texas Instruments to create and market the C2C Chip to Chip Link product.
Learn more about interchip connectivity IP by reading, “Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI…oh my!”
Synopsys-Arteris joint solution for MIPI LLI
Arteris and Synopsys jointly offer analog and digital IP solution to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. This solution consists of the Synopsys DesignWare MIPI M-PHY IP and Arteris FlexLLI LLI digital controller IP.
By providing a collaborative solution that adheres to the LLI specification, Arteris and Synopsys give system-on-chip (SoC) designers access to pre-tested and pre-optimized analog and digital MIPI-based IP that can reduce design cost and accelerate time to market.
Learn more about the Synopsys-Arteris LLI joint solution by reading, “Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs.”
Trademark notice: “C2C”, “Chip to Chip Link”, “C2C Link” and “C2C Interface” are trademarks of Texas Instruments, Inc. Synopsys and DesignWare are registered trademarks or Synopsys, Inc.?