Ramon公司的RC多核心處理器可以與64位的CEVA-X1643DSP集成，這種解決方案可以大大提升并行處理能力，可以被廣泛的應(yīng)用在衛(wèi)星通信領(lǐng)域、探測及科學(xué)探索應(yīng)用領(lǐng)域。
據(jù)2015年5月19日MOUNTAIN VIEW報道，全球DSP主要生產(chǎn)商CEVA公司與Ramon Chip公司宣布合作，雙方將致力于開發(fā)用于空間應(yīng)用的具有抗輻照工藝的ASIC設(shè)計解決方案，目前已有的方案就是集成在RC64 64核心并行處理器中的CEVA-X1643的解決方案，主要面向高要求和高保障的空間應(yīng)用領(lǐng)域。Ramon在RC64處理器中集成了64位CEVA-X1643 DSP核，這種方案可以大大提升運算性能，對于下一代衛(wèi)星通信、地球觀測以及科學(xué)研究或其他應(yīng)用都將會有重要影響，成為核心技術(shù)。
RC64 是 65nm CMOS工藝 并行處理器，提供 384 GOP、 38 GFLOPS和 60 Gbps 的數(shù)據(jù)速率。每個 64 CEVA-X 1643 芯有直接訪問 4 MB 共享內(nèi)存，除了專用內(nèi)存和緩存，包括支持 ECC。核心在運行時被并行任務(wù)的硬件同步器自動管理，有利幾乎完美的實現(xiàn)核芯之間動態(tài)負(fù)載平衡，提高任務(wù)交換效率并降低延遲時間。
Ramon Chip首席執(zhí)行官 Prof. Ran Ginosar說：近二十年來底層處理器技術(shù)在衛(wèi)星都沒有改動大多，對于今天的處理密集型應(yīng)用程序，導(dǎo)致性能不佳。我們新的 RC64 處理器基于 CEVA-X 1643 DSP 承諾要改變這一瓶頸，杰出性能、 可編程性和可擴(kuò)展性可滿足下一代衛(wèi)星系統(tǒng)，多類型最新的衛(wèi)星通信、 研究和觀測應(yīng)用程序所需的大規(guī)模并行處理。
CEVA的營銷副總裁Eran Briman說：很高興能與Ramon Chip公司合作，共同致力于開發(fā)基于CEVA DSP核心的用在衛(wèi)星上的最大規(guī)模的多核并行處理器RC64。其中大規(guī)模多核并行處理能力是高性能空間計算的關(guān)鍵，我們公司的CEVA-X1643性能可以滿足Ramon Chip公司提出的這些苛刻的要求。
CEVA-X 1643 DSP 核心采用單指令多數(shù)據(jù) (SIMD) 的處理能力可提供非常長的指令字 (VLIW)組合。其 32 位編程模型支持高度的并行性，包括每個周期可處理最多八個指令和每個周期 16 SIMD 操作的能力。它配備了高性能基于 AXI 的內(nèi)存子系統(tǒng)，采用完全緩存的指令和數(shù)據(jù)記憶帶 ECC，支持多核和眾核架構(gòu)設(shè)計，并包括Power Scaling Unit (PSU)，提供動態(tài)和漏電功耗的高級電源管理。有關(guān)詳細(xì)信息，請訪問 http://www.ceva-dsp.com/CEVA-X1643。
關(guān)于Ramon Chip公司的介紹
Ramon Chip公司是一家專注于空間應(yīng)用領(lǐng)域具備抗輻照的VLSI/ASIC設(shè)計公司。公司經(jīng)驗證過的RadSafe?核心技術(shù)不僅在空間應(yīng)用復(fù)雜環(huán)境下針對空間粒子效應(yīng)具有很高免疫性和抗輻照性能，還具備很高的集成度，很高的性能，同時保持較低的功耗。公司參與了 2020 年地平線研究項目，包括 VHiSSI、 QI2S 和 MacSpace 。其他信息，請訪問 www.ramon-chips.com。
Ramon Chips Licenses CEVA-X DSP for High Performance Computing for Space Applications
RC64 multi-core processor from Ramon integrates sixty-four CEVA-X1643 DSPs, enabling massively parallel processing for satellite communication, observation and science research applications
MOUNTAIN VIEW, Calif., May 19, 2015 /PRNewswire/ —?CEVA, Inc. (NASDAQ: CEVA), the leading licensor of DSP and IP platforms for cellular, multimedia and connectivity, today announced that Ramon Chips, Ltd., a fabless semiconductor company focused on developing unique Radiation Hardened ASIC solutions for space applications, has licensed the CEVA-X1643 for its RC64 64-core parallel processor, targeting high performance space computations. Ramon will integrate sixty-four CEVA-X1643 DSPs into the RC64 processor, delivering a huge leap in computational power for next-generation satellites deployed for communications, earth observation, science and many other applications.
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RC64 is a 65nm CMOS parallel processor, providing 384 GOPS, 38 GFLOPS and 60 Gbps data rate. Each of the 64 CEVA-X1643 cores has direct access to a 4MB shared memory, in addition to private memories and caches, including support for ECC. The cores are managed at runtime by a hardware synchronizer that automatically manages parallel tasks, enabling nearly-perfect dynamic load balancing among the cores and facilitates task switching at a very high rate and very low latency.
“The underlying processor technologies in satellites have remained mostly unchanged for nearly two decades, resulting in poor performance for today’s processing-intensive applications,” said Prof. Ran Ginosar, CEO at Ramon Chips. “Our new RC64 processor based on the CEVA-X1643 DSP promises to change this, bringing outstanding performance, programmability and scalability to next-generation satellite systems, and enabling the massively parallel processing required for many of the latest satellite communications, research and observation applications.”
“We are excited to work with Ramon Chips on the development of their RC64 64 DSP satellite processor, one of the largest multi-core use cases for our DSPs,” said Eran Briman, vice president of marketing at CEVA. “Massively parallel processing is key for high performance space computing and the CEVA-X1643 delivers exceptional capabilities for the demanding use cases that Ramon is targeting.”
The CEVA-X1643 DSP core, features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. It is equipped with a high performance AXI-based memory sub-system, adopts fully-cached instruction and data memories with ECC, supports multi-core and many-core architectures, and includes an innovative Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. For more information, visit http://www.ceva-dsp.com/CEVA-X1643.
About Ramon Chips
Ramon Chips is a fabless semiconductor company focused on developing unique Radiation Hardened VLSI /ASIC solutions for space applications. Our silicon proven RadSafe? technology provides extreme high immunity to all space radiation effects in LEO, GEO and outer space missions, while maintaining high density, high performance and low power. The company participates in a number of Horizon 2020 research programs, including VHiSSI, QI2S and MacSpace. For additional information, visit www.ramon-chips.com.