Arteris? FlexNoC? provides on-chip connectivity for SoC IP blocks implementing any combination of AMBA? AXI?, AHB?, AHB-Lite, APB?, OCP and PIF protocols.

Arteris FlexNoC is for SoC interconnects with low latency and high throughput requirements. FlexNoC provides support for the features needed by today’s SoCs, such as clock domain conversion, QoS, debug visibility and security.

FlexNoC includes FlexExplorer?for quick?interconnect simulation and iteration?to reduce development time. FlexExplorer’s?OSCI SystemC TLM 2.0 models?can be easily exported for us in industry-leading system-level simulation tools.

Advanced features include:

• FlexMem Memory Scheduler
• On-chip Debug, Tracing, and Statistics Collection
• Multiple Power Domain Management for Dynamic Voltage and Frequency Scaling (DVFS)

Why FlexNoC?

Eliminate Routing Congestion

Arteris NoC IP reduces?routing congestion?by taking advantage of variable link widths and packetization to selectively reduce the number of wires required to meet system throughput and latency constraints.

Whether you are using AMBA AXI3, AXI4, AHB, APB, OCP, PIF or a proprietary protocol, Arteris FlexNoC IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan.

Ease Timing Closure

Timing closure?is simplified by allowing the designer to easily and precisely place pipelines/register slices at specific locations in the interconnect to resolve timing issues. This means timing issues found late in the design cycle can be resolved without having to modify the SoC netlist or re-architect the interconnect.

Speed Time to Market

Arteris FlexNoC makes it easy to develop, verify and iterate interconnect configurations by providing intuitive GUI and scripting interfaces. Out of the box support for all the major IP transaction protocols makes it easy to replace IP to create SoC derivatives or make IP changes late in the design cycle.

Integrated?FlexExplorer simulation?automatically generates OSCI SystemC TLM 2.0?interconnect models?at three levels of abstraction for quick turn-around performance evaluation of interconnect configurations.

Reduce Power Consumption with Clock Gating and Frequency / Voltage Domains (DVFS)

FlexNoC includes support to turn of the clocks of IPs that are not being used. Addition options are available for more advanced clock gating, power domain, and dynamic frequency and voltage scaling (DVFS) capabilities.

Advanced Quality of Service

FlexNoC includes Quality of Service features out of the box that propagates master / initiator QoS information (such as AXI QoS information) through the interconnect and to the target.

This end-to-end QoS solution is for on-chip data flows that must meet concurrent bandwidth and latency requirements from the initiator, through the interconnect, and then through the memory controller.

FlexMem Memory Scheduler

In addition, Arteris offers the optional FlexMem Memory Scheduler to ensure QoS through to the memory controller while reducing on-die routing congestion and timing issues near the memory controller.

Automated Verification for Lowest Risk

In addition to RTL and the three levels of SystemC TLM 2.0 models provided in?FlexExplorer, FlexNoC includes the FlexVerifier Automated Test Environment (ATE) and the FlexVerifier VMM verification environment.