A Complete Set of Tools for System-Level Modeling, Simulation, and Profiling of DSP-based Designs

By raising the level of abstraction by which the entire system is represented to the Electronic System Level (ESL), system modeling addresses the increasing development challenges associated with higher levels of integration and software-rich semiconductor products. These high-level, cycle-accurate representations allow designs to be simulated at high speed while still providing flexibility and visibility into the system.

System modeling facilitates “what-if” analysis of different architectural scenarios so as to achieve the optimal architecture for the target application. It also allows software development (firmware, drivers, and application software) to commence early in the development cycle before the real silicon becomes available. Later, system modeling facilitates hardware/software co-design, integration, and validation.

The?CEVA-Toolbox?and CEVA’s DSP processor core models can be used in conjunction with leading industry system modeling tools and environments, such as Virtualizer from Synopsys and SoC Designer Plus from Carbon Design Systems.

All CEVA-Toolbox simulation and debug capabilities are supported within these ESL environments, allowing CEVA’s DSP processors to be simulated in the context of the entire SoC, including system peripherals, the customer’s proprietary logic, and third-party off-the-shelf processors and modules.

The seamless integration between the?CEVA-Toolbox?and these ESL tools and environments supports extremely sophisticated debug capabilities at the system level. Complete debug interfaces are offered with the ability to perform run-time SoC-level profiling and gain immediate feedback on system behavior. Such debug and profiling capabilities are very powerful for system architects, hardware designers, and software engineers. System architects can carefully design the system and explore different conditions; software engineers are able to view code, set breakpoints, and examine registers and memories; hardware engineers can examine signals, dump waveforms, and trace execution through the system.

The results of using system modeling to perform simulation, debug, verification, and profiling of the customer’s SoC before it is implemented are increased designer productivity, accelerated time to market, and improved product quality.

Key Benefits

• Detailed architectural analysis and exploration facilitates hardware/software partitioning and performance tuning
• Full SoC level simulation, debug, verification, and profiling facilitates full application development, including drivers and system code, before the real silicon is available
• Allows designers to quickly adapt and apply changes to the design before implementing the SoC
• Provides full system verification, including the DSP core(s), system peripherals, the customer’s proprietary logic, and third-party off-the-shelf processors and modules