CEVA-SATA IP Drives State-of-the-Art Storage Systems
As a leading provider of Serial ATA (SATA) IP since 2003, CEVA has a strong track record in licensing and supporting this specialist technology.
CEVA-SATA Device Controller IP
CEVA’s extensive experience with SSD licensees has resulted in a SATA Device Controller IP solution that is tailored for high throughput performance. The optimized Device Command Layer provides hardware off-load for the embedded processor and offers advanced semaphore options for interfacing with system DMA and Cache memory.
The CEVA-SATA Device Controller IP supports the latest SATA3.0 specification for 6Gbps operation. In order to meet the needs of Self Encrypting Drives (SEDs), CEVA has integrated?CEVAnet Partner?AES technology with the CEVA-SATA Device Controller IP to minimize latency and maximize throughput.
CEVA-SATA Host Controller IP
CEVA-SATA AHCI Host Controller and CEVA-SATA Enterprise Host Controller IP packages are available, both supporting SATA3.0 (6Gbps). The AHCI variant is suitable for those applications requiring conformance with standard AHCI software drivers. The Enterprise variant is aimed at embedded applications where the licensee has full control of the software drivers, thereby allowing system customization. In both cases, a feature-rich solution is offered, including hardware assisted FIS-based switching for highest performance in Port Multiplier based systems.
CEVA-SATA IP Target Applications
Target applications for CEVA-SATA Device Controller IP include SSDs and Blu-Ray and other optical storage devices.
Target applications for CEVA-SATA Host Controller IP include Set-Top-Box (STB) and Digital Video Recorders, Media Gateway Servers, netbook and tablet computers, RAID Controllers, and Surveillance Controllers.
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…and many more –?Download the CEVA-SATA Product Brief for more information |
Architectural Highlights
- Multiple system bus options, including AHB-32b, AXI-32b, AXI-64b, and AXI-128b
- Multiple FIFO options within the Transport Layer to accommodate the licensee’s system bus latencies while providing optimized die area
- A comprehensive and flexible PHY Control Layer to interface to multiple PHY/SERDES options, incorporating 8B/10B coding, OOB processing, and PhyInt state machine.