CEVA-TeakLite for High-Volume, Cost-Sensitive Applications
The CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based Harvard architecture, the CEVA-TeakLite family combines small die size, excellent code density, and high processing power.
CEVA-TeakLite block diagram
The most cost-effective member of the CEVA-TeakLite Family, the CEVA-TeakLite, is a fully synthesizable (soft core), process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency. This low-power, single MAC, 16-bit, fixed-point DSP core has been specifically designed to be embedded in highly-integrated System-on-Chip (SoC) devices.
CEVA-TeakLite Supporting Deliverables
The CEVA-TeakLite is supported by a wide range of deliverables, which significantly reduces risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TeakLite designs can also be implemented in an FPGA for prototyping and system integration.
The CEVA-TeakLite is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’sDSP cores?and?Platform Solutions. Visit our?CEVAnet Partners?page for more information.
CEVA-TeakLite Target Applications
Target applications for the CEVA-TeakLite include audio, voice, 2G/2.5G wireless baseband, Power Line Communication (PLC), VoIP, and other signal processing for mobile computing devices, wireless handsets, portable media players, hard disk drives, optical drives, and more.
| Features | Benefits |
|---|---|
High performance
|
High performance makes the CEVA-TeakLite applicable to multiple application domains from audio and voice to baseband |
Native 16-bit
|
Efficient signal processoring supported by a broad range of fully-certified voice and audio codecs |
Easy software development
|
Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market |
| …and many more –?Download the CEVA-TeakLite Product Brief for more information | |
Architectural Highlights
Based on a 16×16-bit multiplier, the CEVA-TeakLite can perform a Multiply-Accumulate (MAC) operation in a single cycle. The CEVA-TeakLite also offers:
- Up to 64KW program memory and 64KW data memory (16-bit words)
- Two parallel 16-bit transfers to/from data memory
- A 36-bit Arithmetic Logic Unit (ALU)
- A 36-bit barrel-shifter
- Four independent 36-bit accumulators
- Automatic saturation on overflow
- See the CEVA-TeakLite-ll Product Brief for more information
The CEVA-TeakLite supports an advanced set of digital signal processing instructions as well as general-purpose microprocessor instructions. The CEVA-TeakLite’s instruction set and programming model are designed for the straightforward generation of compact and efficient code composed of only 16-bit wide instructions.
The CEVA-TeakLite’s unique Instruction Set Architecture (ISA) allows it to efficiently handle applications requiring both DSP and control functions. Dedicated mechanisms are implemented to support Real-Time Operating System (RTOS) requirements, such as nested loops and wide Automatic Context Switching.
Codecs Available
Codecs available directly from CEVA include:
| Vocoders | Audio decoders | Audio encoders |
|---|---|---|
| G.723 | MP3 | MP3 |
| G.729 | MPEG4 AAC-LC | MPEG4 AAC-LC |
| G.711 | HE-AAC V1 | HE-AAC V1 |
| G.726 | WMA8 | SBC |
| G.727 xxxxxx | SBC | |
| G.168 | Dolby Digital (AC3) | |
| G.161 | ||
| AMR-NB | ||
| HR | ||
| FR | ||
| AMR-WB |