Highlights

The CEVA-XC4210 offers a wealth of architectural features as follows:

Fully programmable DSP processor architecture

Two vector processing units – each unit operates on 256-bit vector registers offering a powerful SIMD engine

• Up to 8 simultaneous instructions (8-Way VLIW)
• Efficient DSP support for non-vectorized data
• Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

• 64 16×16-bit MAC operations
• 64 arithmetic operations per cycle
• Over 400 16-bit operations in a cycle

Exceptional power efficiency

• Incorporates Power Scaling Unit – PSU 2.0
• Dedicated power optimized Tightly Coupled Extensions (TCE)
• Enhanced power-optimized pipeline

Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules

• Scalable computation capabilities and memories
• Configurable utilization of optional instruction sets

Uniquely designed for communication applications

• High flexibility SIMD programming model with intra-vector permutation capabilities
• Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more

Tightly Coupled ExtensionsS (TCE)

• A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including: MLD MIMO detector, 3G De-spreader units, DFT,? FFT, Viterbi,
• LLR processing and HARQ combining
• User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
• Offers parallel computing in parallel to the DSP functions
• Offloading the core and lowering its frequency to minimize power consumption

Complete memory subsystem

• Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
• Ensures easy integration and optimal performance in Target SoCs

Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices:

• Advanced power management for both dynamic and leakage power.
• Multiple voltage domains associated with the functional units.

• Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO).

LTE-A Ref. Architecture

CEVA-XC4210 multi-mode LTE-Advanced reference architecture

 

LTE-A Reference Architecture

Based on multiple CEVA-XC processors, CEVA offers a complete multimode LTE-Advanced reference architecture targeting LTE-A Rel-10 Cat-7. The reference architecture leverages on years of accumulated knowledge with CEVA’s Tier-1 baseband licensees, is based on CEVA-XC optimized communication Libraries and addresses the entire PHY layer requirements.

Reference architecture highlights:

• A complete LTE-A PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: LTE-Advanced, TD-LTE-Advanced, HSPA+, TD-SCDMA, and more
• Built around CEVA-XC processors with minimal complementary hardware accelerators
• Offers industry’s most competitive SDR platform in terms of both cost and power consumption
• Supports maximal throughput of LTE-A Rel-10 CAT-7 UE FDD (DL: 300Mbps, UL: 100Mbps) with up to 8×4 MIMO and carrier aggregation of up to two carrier components to a total of 40MHz channel
• High operating margins enabling customer differentiation by software

Wi-Fi 802.11ac Ref. Architecture

CEVA-XC4000 based Wi-Fi 802.11ac reference architecture

 

802.11ac Reference Architecture

Based on a single CEVA-XC4210 processor, CEVA offers a complete Wi-Fi 802.11ac reference architecture targeting mobile stations (STA). The reference architecture was developed together with?Antcor, a member of the CEVA-XCnet partner program?and addresses the entire PHY and lower MAC layers requirements.

Reference architectures highlights:

• Addresses both PHY and Lower-MAC with minimal complementary hardware acceleration
• Built around a single CEVA-XC4210 processor with minimal complementary hardware accelerators
• Offers industry’s most competitive SDR platform in terms of both cost and power consumption
• Supports up to full 160MHz channel bandwidth
• Maximal throughput of 867Mbps (scalable to 1.7Gbps) with up to 4×2 MIMO beam-forming, with 256-QAM support
• Extremely low power solution targeting low power process for mobile Wi-Fi stations (STA)
• High operating margins enabling customer differentiation by software